Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation\nenvironments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x\narea overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened\nbecause TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the\ntriplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules\nand resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level\nsynthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy,\nwhile focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures.\nCompared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34%\nand an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74%with\naverage resource savings of 19%and an average heuristic execution time improvement of 96x.
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